Abstract
To sustain the exponential growth in computing efficiency and throughput, a vast and diverse set of novel potential solutions are being explored at various levels of abstraction. Novel transistor architectures such as gate-all-around nanosheet field-effect transistors (GAAFET) and vertically-stacked complementary transistors (CFET) are being developed to address the limitations of the FinFET technology. To augment CMOS technology, a host of novel materials and devices such as ferromagnets and ferroelectrics are being explored. In most cases, the emerging memory and logic devices are not simple “drop-in” replacements and require novel circuit- and system-level redesign and cross-layer co-optimization. At higher levels of abstraction, novel computing paradigms such as Hyperdimensional, Neurosymbolic, and Probabilistic Computing have been proposed to go beyond what is achievable with the current power- and data-hungry AI systems. Various in-memory and near-memory schemes are also being developed to alleviate the limits imposed by data movement. The diversity and the disruptive nature of the proposed technology and design options pose major challenges for the modeling, design, and technology development of the next generations of computing hardware and to formulate and optimize circuit and architectural designs that can best leverage the hardware of tomorrow.
In this talk, I present our efforts in developing a comprehensive modeling platform for CMOS and Beyond-CMOS technology options and demonstrate how such models can be used for the design and evaluation of the major building blocks of various cognitive Motifs. The technology options that will be discussed include nanosheet GAAFET, back side power delivery, and magnetic and ferroelectric memory devices. Content addressable memories implemented with various technology options will be explored and benchmarked. At a higher level of abstraction, the application of these devices and circuits in Hyperdimensional and Neurosymbolic Computing and Recommendation Models will be explored.
I will conclude my talk by briefly describing our educational innovations/efforts aimed at helping our students better prepare for work and research in this rapidly-changing field.
Bio
Azad Naeemi is a professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. His technical research crosses the boundaries of materials, devices, circuits, and systems, investigating integrated circuits based on conventional and emerging nanoscale devices and interconnects. His educational research includes experiential learning environments and their impact on conceptual understanding of scientific and engineering topics. He serves as the Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) and is the Associate Director for Computation for the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). He is the lead PI of an NSF-funded 6-university collaborative effort on Interactive Visualizations and Simulations for Conceptual Understanding in Quantum and Semiconductor Physics. He is a recipient of the IEEE Electron Devices Society (EDS) Paul Rappaport Award, the Inaugural IEEE Solid-State Circuits Society (SSCS) James Meindl Innovators Award, an NSF CAREER Award, an SRC Inventor Recognition Award, and several best paper awards from international conferences. In 2023, he received the Faculty Honors Class of 1934 Outstanding Innovative Use of Educational Technology Award at Georgia Tech.
